sequentially access its data. The simple sequential access dramatically reduces active pin
count, facilitates hardware layout, increases system reliability, minimizes switching noise, and
reduces package size. The device is optimized for use in many commercial and industrial appli-
cations where high-density, low-pin count, low-voltage and low-power are essential.
To allow for simple in-system reprogrammability, the AT45DB321D does not require high input
voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for
both the program and read operations. The AT45DB321D is enabled through the chip select pin
(CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output
(SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
2. Pin Configurations and Pinouts
Figure 2-1. MLF(1) (VDFN) Top View
Figure 2-2. SOIC Top View
1
2
3
4
8
7
6
5
SI
SCK
SO
SI
SCK
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
GND
VCC
WP
RESET
CS
RESET
CS
Note:
1. The metal pad on the bottom of the MLF
package is floating. This pad can be a “No
Connect” or connected to GND.
Figure 2-3. DataFlash Card(1)
Top View through Package
Figure 2-4. TSOP Top View: Type 1
RDY/BUSY
RESET
WP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
7
6 5 4 3 2 1
3
NC
4
NC
5
VCC
GND
NC
6
7
8
NC
9
NC
10
11
12
13
14
CS
SCK
SI
Note:
1. See AT45DCB004D Datasheet.
SO
Note:
TSOP package is not recommended for new designs. Future die
shrinks will support 8-pin packages only.
2
AT45DB321D
3597J–DFLASH–4/08
ATMEL [ ATMEL ]
