When the device is shipped from Atmel, the most significant page of the memory array may not
be erased. In other words, the contents of the last page may not be filled with FFH.
2. Pin Configurations and Packages
Table 2-1.
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Pin Configurations
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write Protect Pin
Chip Reset
Ready/Busy
Figure 2-1.
TSOP Top View Type 1
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2-2.
CASON – Top View through Package
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
Figure 2-3.
SI
SCK
RESET
CS
8-SOIC
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
SO
GND
VCC
WP
Figure 2-4.
28-SOIC
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2-5.
CBGA Top View
through Package
1
2
3
A
NC
NC
VCC
B
SCK
GND
C
CS RDY/BSY WP
D
SO
SI
NC
RESET
NC
E
NC
Note:
1. The next generation DataFlash devices will not be
offered in 28-SOIC package, therefore, this pack-
age is not recommended for new designs.
2
AT45DB041B
3443D–DFLSH–2/08
ATMEL [ ATMEL CORPORATION ]
