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AT40K05LV-3DQI 参数 Datasheet PDF下载

AT40K05LV-3DQI图片预览
型号: AT40K05LV-3DQI
PDF下载: 下载PDF文件 查看货源
内容描述: 5K - 50K盖茨FPGA协处理器与FreeRAM [5K - 50K Gates Coprocessor FPGA with FreeRAM]
分类和应用: 现场可编程门阵列可编程逻辑异步传输模式ATM
文件页数/大小: 67 页 / 1491 K
品牌: ATMEL [ ATMEL ]
 浏览型号AT40K05LV-3DQI的Datasheet PDF文件第59页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第60页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第61页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第62页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第63页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第64页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第65页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第67页  
352C1 SBGA  
A1 BALL  
CORNER  
A1 BALL CORNER  
D
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9 8 7 6 5 4 3 2 1  
A
B
b  
C
D
E
F
G
A1 BALL I.D.  
H
J
K
L
M
N
E
P
R
T
e
U
V
W
Y
AA  
AB  
AC  
AD  
AE  
AF  
e
Top View  
Bottom View  
Die Side  
A
A2  
A1  
Section View  
SEATING PLANE  
Side View  
COMMON DIMENSIONS  
(Unit of Measure = mm)  
MIN  
MAX  
NOM  
35.0 BSC  
35.0 BSC  
26 x 26  
NOTE  
SYMBOL  
D
E
Matrix Size  
A
A1  
A2  
b∅  
e
1.70  
0.35  
0.25  
0.60  
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing  
MO-192, Variation BAR-2, for additional information.  
2. JEDEC variations are based on fully populated ball arrays. Arrays  
can be depopulated as desired by removing balls from the fully populated  
array.  
1.10  
0.90  
0.75  
1.27 BSC  
3/29/02  
TITLE  
DRAWING NO.  
REV.  
2325 Orchard Parkway  
San Jose, CA 95131  
352C1, 352-ball, 35 x 35, Enhanced, Low-profile  
Square Ball Grid Array Package (SBGA)  
352C1  
A
R
66  
AT40K/AT40KLV Series FPGA  
0896CFPGA04/02  
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