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AT24C64CN-SH-T 参数 Datasheet PDF下载

AT24C64CN-SH-T图片预览
型号: AT24C64CN-SH-T
PDF下载: 下载PDF文件 查看货源
内容描述: 2线串行EEPROM 32K ( 4096 ×8 ), 64K ( 8192 ×8 ) [2-Wire Serial EEPROM 32K (4096 x 8) 64K (8192 x 8)]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 28 页 / 814 K
品牌: ATMEL [ ATMEL ]
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4. Device Operation  
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external  
device. Data on the SDA pin may change only during SCL low time periods (refer to Data Valid-  
ity timing diagram). Data changes during SCL high periods will indicate a start or stop condition  
as defined below.  
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which  
must precede any other command (refer to Start and Stop Definition timing diagram).  
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a  
read sequence, the stop command will place the EEPROM in a standby power mode (refer to  
Start and Stop Definition timing diagram).  
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the  
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-  
edge that it has received each word.  
STANDBY MODE: The AT24C32C/64C features a low power standby mode which is enabled:  
a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal  
operations.  
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire  
part can be protocol reset by following these steps:  
(a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit  
condition as shown below. The device is ready for next communication after above steps have  
been completed.  
Figure 4-1. Software Reset  
Dummy Clock Cycles  
Start bit  
Stop bit  
Start bit  
1
2
3
8
9
SCL  
SDA  
6
AT24C32C/64C  
5298A–SEEPR–1/08