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AT24C32-10PC-2.5 参数 Datasheet PDF下载

AT24C32-10PC-2.5图片预览
型号: AT24C32-10PC-2.5
PDF下载: 下载PDF文件 查看货源
内容描述: 2线串行EEPROM [2-Wire Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 15 页 / 240 K
品牌: ATMEL [ ATMEL ]
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Absolute Maximum Ratings*  
*NOTICE:  
Stresses beyond those listed under “Absolute  
Maximum Ratings” may cause permanent dam-  
age to the device. This is a stress rating only and  
functional operation of the device at these or any  
other conditions beyond those indicated in the  
operational sections of this specification is not  
implied. Exposure to absolute maximum rating  
conditions for extended periods may affect  
device reliability.  
Operating Temperature.................................. -55°C to +125°C  
Storage Temperature..................................... -65°C to +150°C  
Voltage on Any Pin  
with Respect to Ground.....................................-1.0V to +7.0V  
Maximum Operating Voltage........................................... 6.25V  
DC Output Current........................................................ 5.0 mA  
Block Diagram  
Device Addressing section). When the pins are not hard-  
wired, the default A2, A1, and A0 are zero.  
Pin Description  
SERIAL CLOCK (SCL): The SCL input is used to positive  
edge clock data into each EEPROM device and negative  
edge clock data out of each device.  
WRITE PROTECT (WP): The write protect input, when tied  
to GND, allows normal write operations. When WP is tied  
high to VCC, all write operations to the upper quandrant  
(8/16K bits) of memory are inhibited. If left unconnected,  
WP is internally pulled down to GND.  
SERIAL DATA (SDA): The SDA pin is bidirectional for  
serial data transfer. This pin is open-drain driven and may  
be wire-ORed with any number of other open-drain or open  
collector devices.  
Memory Organization  
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1  
and A0 pins are device address inputs that are hard wired  
or left not connected for hardware compatibility with  
AT24C16. When the pins are hardwired, as many as eight  
32K/64K devices may be addressed on a single bus sys-  
tem (device addressing is discussed in detail under the  
AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is  
internally organized as 256 pages of 32 bytes each. Ran-  
dom word addressing requires a 12/13 bit data word  
address.  
AT24C32/64  
2