WRITE ALL (WRAL):
The write all (WRAL) instruction programs all memory locations with the data patterns specified in
the instruction. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a
minimum of 250ns (t
CS
). The WRAL instruction is valid only at V
CC
= 5.0V
±10%.
ERASE/WRITE DISABLE (EWDS):
To protect against accidental data disturbance, the erase/write disable (EWDS)
instruction disables all programming modes, and should be executed after all programming operations. The operation of the
READ instruction is independent of both the EWEN and EWDS instructions, and can be executed at any time.
3.
Timing Diagrams
Figure 3-1.
Synchronous Data Timing
Note:
1. This is the minimum SK period
Table 3-1.
Organization Key for Timing Diagrams
Atmel AT93C56B (2K)
I/O
A
N
D
N
x8
A
8
D
7
x 16
A
7
D
15
Atmel AT93C66B (4K)
x8
A
8
D
7
x 16
A
7
D
15
Notes:
1. A
8
is a don’t-care value, but the extra clock is required
2. A
7
is a don’t-care value, but the extra clock is required
6
Atmel AT93C56B/66B
8735A–SEEPR–1/11
ATMEL [ ATMEL CORPORATION ]
