Block Diagram
Figure 1. TSC695F Block Diagram
32-bit
Integer
Unit
DMA
TAP
DMA Ctrl
Arbiter
32/64-bit
Floating-Point
Unit
Clock
&
Parity
Gen./Chk.
Reset
Access
Controller
Parity
Managt
Mem Ctrl
Gen./Chk.
Wait State
Controller
Ready/Busy
Add.+Size+ASI
Address
Interface
Error
Managt
Real Time Clock
Timer
Watch
Dog
General Purpose
Timer
EDAC
Data+Check bits
Parities
Interrupt
General Purpose
Interface
UART B
UART A
Parity
Gen./Check.
Controller
Interrupts
GPI bits
RxD, TxD
Pin Descriptions
For pin assignment, refer to package section.
Table 1. Pin Descriptions
Signal
Type
Active
Description
RA[31:0]
RAPAR
RASI[3:0]
RSIZE[1:0]
RASPAR
CPAR
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
32-bit registered address bus
Registered address bus parity
4-bit registered address space identifier
2-bit registered bus transaction size
Registered ASI and SIZE parity
Control bus parity
Output buffer: 400 pF
High
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High
High
D[31:0]
CB[6:0]
DPAR
32-bit data bus
7-bit check-bit bus
High
High
Low
High
High
High
Low
High
Data bus parity
RLDSTO
ALE
Registered atomic load-store
Address latch enable
Data transfer
DXFER
LOCK
I/O
I/O
I/O
I/O
I/O
Bus lock
RD
Read access
WE
Write enable
WRT
Advanced write
MHOLD+FHOLD
+BHOLD+FCCV
MHOLD
O
Low
Memory bus hold
MDS
O
O
I
Low
Low
Low
Memory data strobe
-
MEXC
Memory exception
-
PROM8
BA[1:0]
Select 8-bit wide PROM
Latched address used for 8-bit wide boot PROM
PROM chip select
-
O
O
I
-
ROMCS
ROMWRT
MEMCS[9:0]
MEMWR
Low
Low
Low
Low
-
ROM write enable
-
O
O
Memory chip select
Output buffer: 400 pF
Output buffer: 400 pF
Memory write strobe
2
TSC695F
4118J–AERO–08/04
ATMEL [ ATMEL ]
