TSC695F
Table 3. System Registers Address Map (Continued)
System Register Name
Address
Memory Configuration Register
I/O Configuration Register
MCNFR
0x 01F8 0010
0x 01F8 0014
0x 01F8 0018
0x 01F8 0020
0x 01F8 0024
0x 01F8 0028
0x 01F8 002C
0x 01F8 0044
0x 01F8 0048
0x 01F8 004C
0x 01F8 0050
0x 01F8 0054
0x 01F8 0060
0x 01F8 0064
0x 01F8 0080
0x 01F8 0084
0x 01F8 0088
0x 01F8 008C
0x 01F8 0098
0x 01F8 00A8
0x 01F8 00AC
0x 01F8 00E0
0x 01F8 00E4
0x 01F8 00E8
IOCNFR
WSCNFR
APS1BR
APS1ER
APS2BR
APS2ER
INTSHR
INTPDR
INTMKR
INTCLR
INTFCR
WDOGTR
WDOGST
RTCCR
Waitstate Configuration Register
Access Protection Segment 1 Base Register
Access Protection Segment 1 End Register
Access Protection Segment 2 Base Register
Access Protection Segment 2 End Register
Interrupt Shape Register
Interrupt Pending Register
Interrupt Mask Register
Interrupt Clear Register
Interrupt Force Register
Watchdog Timer Register
Watchdog Timer Trap Door Set
Real Time Clock Timer <Counter> Register
Real Time Clock Timer <Scaler> Register
General Purpose Timer <Counter> Register
General Purpose Timer <Scaler> Register
Timers Control Register
RTCSR
GPTCR
GPTSR
TIMCTR
GPICNFR
GPIDATR
UARTAR
UARTBR
UARTSR
General Purpose Interface Configuration Register
General Purpose Interface Data Register
UART ’A’ Rx & Tx Register
UART ’B’ Rx & Tx Register
UART Status Register
Wait-state and Time-out
Generator
It is possible to control the wait-state generation by programming a Wait-state Configu-
ration Register. The maximum programmable number of wait-states is applied by
default at reset.
It is possible to program the number of wait-states for the following combinations:
–
–
–
–
RAM read and write
PROM read and write (i.e. EEPROM or Flash write)
Exchange Memory read/write
Four individual I/O peripherals read/write
A bus time-out function of 256 system clock cycles is provided for the bus ready con-
trolled memory areas, i.e., the Extended PROM, Exchange Memory, Extended RAM,
7
4118J–AERO–08/04
ATMEL [ ATMEL ]
