• Bit 7-4 - Reserved bits
These bits are reserved and will always read as zero.
• Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag
This bit is set when a first time-out occurs in the Watchdog Timer and if the WDEWIE bit is
enabled. WDEWIF is automatically cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF can be cleared by writing a logic one to the flag.
When the I-bit in SREG and WDEWIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 2 - WDEWIE: Watchdog Early Warning Interrupt Enable
When this bit has been set by software, an interrupt will be generated on the watchdog interrupt
vector when the Early warning flag is set to one by hardware.
• Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider
– WCLKD = 0 : ClkWDT = Clk128k
– WCLKD = 1 : ClkWDT = Clk128k / 3
– WCLKD = 2 : ClkWDT = Clk128k / 5
– WCLKD = 3 : ClkWDT = Clk128k / 7
58
AT90USB82/162
7707D–AVR–07/08
ATMEL [ ATMEL ]
