AT90USB82/162
sponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the
flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. Two consecutives
times-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will
clear WDIE and WDIF automatically by hardware : the Watchdog goes to System Reset Mode.
This is useful for keeping the Watchdog Timer security while using the interrupt. To reinitialize
the Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should how-
ever not be done within the interrupt service routine itself, as this might compromise the safety-
function of the Watchdog System Reset mode. If the interrupt is not executed before the next
time-out, a System Reset will be applied.
Table 9-5.
Watchdog Timer Configuration
WDTON (Fuse)
WDE
WDIE
Mode
Action on 2x Time-out
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
0
0
1
0
1
0
Stopped
None
Interrupt Mode
System Reset Mode
Interrupt
Reset
Interrupt and System
Reset Mode
Interrupt, then go to
System Reset Mode
1 (unprogrammed)
0 (programmed)
1
x
1
x
System Reset Mode
Reset
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 9-6 on page 59.
9.9.2
Watchdog Timer Clock Divider Register - WDTCKD
Bit
7
6
5
4
3
2
1
0
-
-
-
-
WDE-
WIF
WDEW-
IE
WCLKD
1
WCLKD
0
WDTCKD
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
57
7707D–AVR–07/08
ATMEL [ ATMEL ]
