Figure 6-4. PLL Clocking System
PLLE
PLOCK
Lock
Detector
clk
2MHz
clk
USB (48MHz)
PLL clock
Prescaler
PLL
24x
XTAL1
OSCILLATORS
XTAL2
System Clock
RC OSCILLATOR
8 MHz
Watchdog
OSCILLATOR
6.11.2
PLL Control and Status Register – PLLCSR
Bit
7
6
5
4
3
2
1
0
$29 ($29)
Read/Write
Initial Value
PLLP2
PLLP1
PLLP0
PLLE
PLOCK
PLLCSR
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0/1
R
0
• Bit 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90USB64/128 and always read as zero.
• Bit 4..2 – PLLP2:0 PLL prescaler
These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the
PLL.
Table 6-13. PLL input prescaler configurations
Clock Division
Factor
External XTAL required for USB
operation (MHz)
PLLP2
PLLP1
PLLP0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
2
3
6
4
8
6
12
16
-
8
Reserved
Reserved
-
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started.
50
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
