AT90USB64/128
Table 6-12. Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6.11 PLL
The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL
input is generated from an external low-frequency (the crystal oscillator or external clock input
pin from XTAL1).
6.11.1
Internal PLL for USB interface
The internal PLL in AT90USB64/128 generates a clock frequency that is 24x multiplied from
nominally 2 MHz input. The source of the 2 MHz PLL input clock is the output of the internal PLL
clock prescaler that generates the 2 MHz (See Section 6.11.2 for PLL interface).
49
7593A–AVR–02/06
ATMEL [ ATMEL ]
