Figure 5-3. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address valid
Compute Address
Address
Data
WR
Data
RD
Memory Access Instruction
Next Instruction
5.3
EEPROM Data Memory
The AT90USB64/128 contains 2K/4K bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page 382, page 387, and page 371 respectively.
5.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 5-3. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page 27. for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
5.3.2
The EEPROM Address Register – EEARH and EEARL
Bit
15
14
13
12
11
10
9
8
–
–
–
–
EEAR11
EEAR3
EEAR10
EEAR2
EEAR9
EEAR1
EEAR8
EEAR0
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEARL
22
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
