AT90USB64/128
Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
OCRnx
TOP
OCFnx
15.8 8-bit Timer/Counter Register Description
15.8.1
Timer/Counter Control Register A – TCCR2A
Bit
7
6
5
4
3
2
–
1
0
COM2A
1
COM2A
0
COM2B
1
COM2B
0
–
WGM2
1
WGM2
0
TCCR2A
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 15-1 shows the COM2A1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
Table 15-1. Compare Output Mode, non-PWM Mode
COM2A1
COM2A0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.
Toggle OC2A on Compare Match
Clear OC2A on Compare Match
Set OC2A on Compare Match
161
7593A–AVR–02/06
ATMEL [ ATMEL ]
