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Figure 14-1. 16-bit Timer/Counter Block Diagram(1)
Count
TOVn
(Int.Req.)
Clear
Control Logic
Direction
Clock Select
TCLK
Edge
Detector
Tn
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
= 0
OCFnA
(Int.Req.)
Waveform
OCnA
=
Generation
OCRnA
OCFnB
(Int.Req.)
Fixed
TOP
Values
Waveform
OCnB
=
Generation
OCRnB
OCFnC
(Int.Req.)
Waveform
OCnC
=
Generation
OCRnC
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
Noise
Canceler
ICPn
ICRn
TCCRnA
TCCRnB
TCCRnC
Note:
1. Refer to Figure 1-1 on page 3, Table 10-6 on page 81, and Table 10-9 on page 84 for
Timer/Counter1 and 3 and 3 pin placement and description.
14.1.1
Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-
ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 120. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the
Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these
registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clk ).
n
T
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener-
ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C).
119
7593A–AVR–02/06
ATMEL [ ATMEL ]
