The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
13.8.4
13.8.5
13.8.6
Output Compare Register A – OCR0A
Bit
7
6
5
4
3
2
1
0
OCR0A[7:0]
OCR0A
Read/Write
Initial Value
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
Output Compare Register B – OCR0B
Bit
7
6
5
4
3
2
1
0
OCR0B[7:0]
OCR0B
Read/Write
Initial Value
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
Timer/Counter Interrupt Mask Register – TIMSK0
Bit
7
6
5
4
–
R
0
3
–
R
0
2
1
0
–
–
–
OCIE0B
R/W
0
OCIE0A
R/W
0
TOIE0
R/W
0
TIMSK0
Read/Write
Initial Value
R
0
R
0
R
0
• Bits 7..3, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
116
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
