Features
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Utilizes the
AVR
®
Enhanced RISC Architecture
AVR
- High Performance and Low Power RISC Architecture
118 Powerful Instructions - Most Single Clock Cycle Execution
2K bytes of In-System Programmable ISP Flash
– SPI Serial Interface for In-System Programming
– Endurance: 1,000 Write/Erase Cycles
128 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
128 bytes Internal RAM
32 x 8 General Purpose Working Registers
– 3 AT90S/LS2323 Programmable I/O Lines
– 5 AT90S/LS2343 Programmable I/O Lines
V
CC
: 4.0 - 6.0V AT90S2323/AT90S2343
V
CC
: 2.7 - 6.0V AT90LS2323/AT90LS2343
Power-On Reset Circuit
Speed Grades: 0 - 10 MHz AT90S2323/AT90S2343
Speed Grades: 0 - 4 MHz AT90LS2323/AT90LS2343
Up to 10 MIPS Throughput at 10 MHz
One 8-Bit Timer/Counter with Separate Prescaler
External and Internal Interrupt Sources
Programmable Watchdog Timer with On-Chip Oscillator
Low Power Idle and Power Down Modes
Programming Lock for Flash Program and EEPROM Data Security
Selectable On-Chip RC Oscillator
8-Pin Device
8-Bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
AT90S2323
AT90LS2323
AT90S2343
AT90LS2343
Preliminary
AT90S/LS2323
Description
The AT90S/LS2323 and AT90S/LS2343 is a low-power CMOS 8-bit microcontrollers
based on the
AVR
®
enhanced RISC architecture. By executing powerful instructions
in a single clock cycle, the AT90S/LS2323 and AT90S/LS2343 achieves throughputs
approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
Pin Configuration
PDIP/SOIC
RESET
(CLOCK) PB3
PB4
GND
1
2
3
4
8
7
6
5
VCC
RESET
PB2 (SCK/T0)
XTAL1
PB1 (MISO/INT0) XTAL2
PB0 (MOSI)
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
AT90S/LS2343
AT90S/LS2323
Rev. 1004AS–05/98
Note: This is a summary document. For the complete 34 page
document, please visit our website at
www.atmel.com
or e-mail at
literature@atmel.com
and request literature #1004A.
1
ATMEL [ ATMEL CORPORATION ]
