AT90S/LS2323 and AT90S/LS2343
AT90S/LS2323 and AT90S/LS2343 Instruction Set Summary
Mnemonics
Operands
Description
Operation
Rd
←
Rd + Rr
Rd
←
Rd + Rr + C
Rdh:Rdl
←
Rdh:Rdl + K
Rd
←
Rd
−
Rr
Rd
←
Rd
−
K
Rdh:Rdl
←
Rdh:Rdl
−
K
Rd
←
Rd
−
Rr
−
C
Rd
←
Rd
−
K
−
C
Rd
←
Rd
•
Rr
Rd
←
Rd
•
K
Rd
←
Rd v Rr
Rd
←
Rd v K
Rd
←
Rd
⊕
Rr
Rd
←
$FF
−
Rd
Rd
←
$00
−
Rd
Rd
←
Rd v K
Rd
←
Rd
•
($FF
−
K)
Rd
←
Rd + 1
Rd
←
Rd
−
1
Rd
←
Rd
•
Rd
Rd
←
Rd
⊕
Rd
Rd
←
$FF
PC
←
PC + k + 1
PC
←
Z
PC
←
PC + k + 1
PC
←
Z
PC
←
STACK
PC
←
STACK
if (Rd = Rr) PC
←
PC + 2 or 3
Rd
−
Rr
Rd
−
Rr
−
C
Rd
−
K
if (Rr(b)=0) PC
←
PC + 2 or 3
if (Rr(b)=1) PC
←
PC + 2 or 3
if (P(b)=0) PC
←
PC + 2 or 3
if (R(b)=1) PC
←
PC + 2 or 3
if (SREG(s) = 1) then PC
←
PC + k + 1
if (SREG(s) = 0) then PC
←
PC + k + 1
if (Z = 1) then PC
←
PC + k + 1
if (Z = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (N = 1) then PC
←
PC + k + 1
if (N = 0) then PC
←
PC + k + 1
if (N
⊕
V= 0) then PC
←
PC + k + 1
if (N
⊕
V= 1) then PC
←
PC + k + 1
if (H = 1) then PC
←
PC + k + 1
if (H = 0) then PC
←
PC + k + 1
if (T = 1) then PC
←
PC + k + 1
if (T = 0) then PC
←
PC + k + 1
if (V = 1) then PC
←
PC + k + 1
if (V = 0) then PC
←
PC + k + 1
if ( I = 1) then PC
←
PC + k + 1
if ( I = 0) then PC
←
PC + k + 1
Flags
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clock
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
4
4
1/2
1
1
1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBIW
Rdl,K
Subtract Immediate from Word
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
(continued)
8
ATMEL [ ATMEL CORPORATION ]
