Port B as General Digital I/O
All eight pins in Port B have equal functionality when used as digital I/O pins.
PBn, General I/O pin: The DDBn bit in the DDRB Register selects the direction of this
pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero),
PBn is configured as an input pin. If PORTBn is set (one) and the pin is configured as an
input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off,
PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The
Port B pins are tri-stated when a reset condition becomes active, even if the clock is not
active.
Table 9. DDBn Effect on Port B Pins
DDBn
PORTBn
I/O
Pull-up
No
Comment
0
0
1
1
0
1
0
1
Input
Tri-state (High-Z)
Input
Yes
PBn will source current if ext. pulled low.
Push-pull Zero Output
Push-pull One Output
Output
Output
No
No
Note:
n: 7,6...0, pin number.
Alternate Functions of Port B The alternate pin functions of Port B are:
• SCK – Port B, Bit 7
SCK, Clock Input pin for memory up/downloading.
• MISO – Port B, Bit 6
MISO, Data Output pin for memory uploading.
• MOSI – Port B, Bit 5
MOSI, Data Input pin for memory downloading.
• AIN1 – Port B, Bit 1
AIN1, Analog Comparator Negative Input. When configured as an input (DDB1 is
cleared [zero]) and with the internal MOS pull-up resistor switched off (PB1 is cleared
[zero]), this pin also serves as the negative input of the On-chip Analog Comparator.
• AIN0 – Port B, Bit 0
AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared
[zero]) and with the internal MOS pull-up resistor switched off (PB0 is cleared [zero]),
this pin also serves as the positive input of the On-chip Analog Comparator.
30
AT90S1200
0838H–AVR–03/02
ATMEL [ ATMEL ]
