Table 69. Program Lock Bits of the SSB
Program Lock Bits
Security
level
LB0
U
LB1 Protection Description
1
2
3
U
U
P
No program lock features enabled.
P
ISP programming of the Flash is disabled.
X
Same as 2, also verify through ISP programming interface is disabled.
Note:
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: don’t care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
Flash Memory Status
AT89C51RB2/RC2 parts are delivered in standard with the ISP boot in the Flash mem-
ory. After ISP or parallel programming, the possible contents of the Flash memory are
summarized on Figure 35.
Figure 35. Flash Memory Possible Contents
7FFFh
T89C51RC2 32KB
3FFFh T89C51RB2 16KB
Virgin
or
Application
Virgin
Application
Virgin
or
Application
Application
Dedicated
ISP
Dedicated
ISP
0000h
After Parallel
Programming
After Parallel
Programming
After ISP
Default
After ISP
Memory Organization
In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memory address
space is filled by internal Flash.
When the EA pin is high, the processor fetches instructions from internal program Flash.
Bus expansion for accessing program memory from 16K or 32K upward automatic since
external instruction fetches occur automatically when the program counter exceeds
3FFFh (16K) or 7FFFh (32K). If the EA pin is tied low, all program memory fetches are
from external memory.
90
AT89C51RB2/RC2
4180E–8051–10/06
ATMEL [ ATMEL ]
