AT89C51RB2/RC2
Table 67. Default Values
Mnemonic Definition
Default value Description
SBV
HSB
BSB
SSB
Software Boot Vector
FCh
101x 1011b
0FFh
Hardware security Byte
Boot Status Byte
Software Security Byte
FFh
Copy of the Manufacturer Code
Copy of the Device ID #1: Family Code
Copy of the Device ID #2: memories
size and type
58h
D7h
F7h
FBh
ATMEL
C51 X2, Electrically Erasable
AT89C51RB2/RC2 32KB
AT89C51RB2/RC2 16 KB
Copy of the Device ID #3: name and
revision
AT89C51RB2/RC2 32KB,
Revision 0
EFh
FFh
AT89C51RB2/RC2 16 KB,
Revision 0
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 67 and Table 69.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 68. Software Security Byte
7
-
6
-
5
-
4
-
3
-
2
-
1
0
LB1
LB0
Bit
Bit
Number
Mnemonic Description
Reserved
Do not clear this bit.
7
6
5
4
3
2
-
Reserved
Do not clear this bit.
-
-
-
-
-
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
User Memory Lock Bits
1-0
LB1-0
see Table 69
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 69.
89
4180E–8051–10/06
ATMEL [ ATMEL ]
