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89C51RC2-UL 参数 Datasheet PDF下载

89C51RC2-UL图片预览
型号: 89C51RC2-UL
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有16K / 32K字节的闪存 [8-bit Microcontroller with 16K/ 32K Bytes Flash]
分类和应用: 闪存微控制器
文件页数/大小: 127 页 / 1478 K
品牌: ATMEL [ ATMEL ]
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AT89C51RB2/RC2  
Registers  
Table 22. CMOD Register  
CMOD – PCA Counter Mode Register (D9h)  
7
6
5
-
4
-
3
-
2
1
0
CIDL  
WDTE  
CPS1  
CPS0  
ECF  
Bit  
Bit  
Number  
Mnemonic Description  
Counter Idle Control  
7
6
CIDL  
Cleared to program the PCA Counter to continue functioning during idle Mode.  
Set to program PCA to be gated off during idle.  
Watchdog Timer Enable  
WDTE  
Cleared to disable Watchdog Timer function on PCA Module 4.  
Set to enable Watchdog Timer function on PCA Module 4.  
Reserved  
5
4
-
-
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
3
2
-
The value read from this bit is indeterminate. Do not set this bit.  
CPS1  
PCA Count Pulse Select  
CPS1 CPS0 Selected PCA input  
0
0
1
1
0
1
0
1
Internal clock FCLK PERIPH/6  
Internal clock FLK PERIPH/2  
1
0
CPS0  
ECF  
Timer 0 Overflow  
External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)  
PCA Enable Counter Overflow Interrupt  
Cleared to disable CF bit in CCON to inhibit an interrupt.  
Set to enable CF bit in CCON to generate an interrupt.  
Reset Value = 00XX X000b  
Not bit addressable  
The CMOD register includes three additional bits associated with the PCA.  
The CIDL bit which allows the PCA to stop during idle mode.  
The WDTE bit which enables or disables the watchdog function on Module 4.  
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in  
the CCON SFR) to be set when the PCA timer overflows.  
The CCON register contains the run control bit for the PCA and the flags for the PCA  
timer (CF) and each Module (see Table 23).  
Bit CR (CCON. 6) must be set by software to run the PCA. The PCA is shut off by  
clearing this bit.  
Bit CF: The CF bit (CCON. 7) is set when the PCA counter overflows and an  
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can  
only be cleared by software.  
Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1,  
etc. ) and are set by hardware when either a match or a capture occurs. These flags  
also can only be cleared by software.  
33  
4180E–8051–10/06  
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