Registers
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
Table 43. Priority Level Bit Values
IPH. x
IPL. x
Interrupt Level Priority
0
0
1
1
0
1
0
1
0 (Lowest)
1
2
3 (Highest)
If two interrupt requests of different priority levels are received simultaneously, the
request of higher-priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
56
AT89C51RB2/RC2
4180E–8051–10/06
ATMEL [ ATMEL ]
