Table 42. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
-
6
-
5
-
4
3
2
1
0
BRR
TBCK
RBCK
SPD
SRC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
-
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Run Control bit
4
3
2
1
BRR
TBCK
RBCK
SPD
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2
mode).
0
SRC
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b
Not bit addressablef
54
AT89C51RB2/RC2
4180E–8051–10/06
ATMEL [ ATMEL ]
