Table 40. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic
Description
Timer 2 overflow Flag
7
6
TF2
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
EXF2
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
Receive Clock bit for UART
5
4
RCLK
TCLK
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
3
2
1
EXEN2
TR2
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
C/T2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
timer 2 overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
0
CP/RL2#
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
52
AT89C51RB2/RC2
4180C–8051–12/03
ATMEL [ ATMEL ]
