AT89C51RB2/RC2
Table 33. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
FE
SMOD0 must be set to enable access to the FE bit.
7
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SM0
SM1
SMOD0 must be cleared to enable access to the SM0 bit.
Serial port Mode bit 1
SM0 SM1
Mode
Baud Rate
0
0
1
1
0
1
0
1
Shift Register FXTAL/12 (or FXTAL /6 in mode X2)
6
5
8-bit UART
9-bit UART
9-bit UART
Variable
XTAL/64 or FXTAL/32
Variable
F
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
SM2
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
4
3
REN
TB8
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
2
RB8
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
1
0
TI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 18.
and Figure 19. in the other modes.
RI
Reset Value = 0000 0000b
Bit addressable
49
4180C–8051–12/03
ATMEL [ ATMEL ]
