–
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-down mode and may
continue for a number of clock cycles before the internal reset algorithm takes
control. Reset initializes the AT89C5132 and vectors the CPU to address 0000h.
Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is
possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the
instruction immediately following the instruction that activated the Power-down mode should
not write to a Port pin or to the external RAM.
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM
content.
11.5 Registers
Table 18. PCON Register
PCON (S:87h) – Power Configuration Register
7
6
5
-
4
-
3
2
1
0
SMOD1
SMOD0
GF1
GF0
PD
IDL
Bit
Bit Number Mnemonic Description
Serial Port Mode Bit 1
Set to select double baud rate in mode 1,2 or 3.
7
6
SMOD1
SMOD0
-
Serial Port Mode Bit 0
Set to select FE bit in SCON register.
Clear to select SM0 bit in SCON register.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
5 - 4
General-Purpose Flag 1
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
3
GF1
General-Purpose Flag 0
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
2
1
GF0
PD
Power-Down Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.
Idle Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
0
IDL
If IDL and PD are both set, PD takes precedence.
Reset Value = 00XX 0000b
48
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
