Figure 31. Timer 0 and Timer 1 Clock Controller and Symbols
PER
CLOCK
PER
CLOCK
0
1
0
1
Timer 0
Clock
Timer 1
Clock
OSC
CLOCK
OSC
CLOCK
÷ 2
÷ 2
T0X2
CKCON.1
T1X2
CKCON.2
TIM0
TIM1
CLOCK
CLOCK
Timer 0 Clock Symbol
Timer 1 Clock Symbol
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation.
Figure 32, Figure 34, Figure 36, and Figure 38 show the logical configuration of each
mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Table 82) and bits 0, 1,
4 and 5 of TCON register (see Table 81). TMOD register selects the method of Timer
gating (GATE0), Timer or Counter operation (C/T0#) and mode of operation (M10 and
M00) according to Table 78. TCON register provides Timer 0 control functions: overflow
flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-
rupt request.
It is important to stop Timer/Counter before changing mode.
Table 78. Timer/counter 0 Operating Modes
M10
M00
Mode
Operation
0
0
1
0
1
0
0
1
2
8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).
16-bit Timer/Counter.
8-bit auto-reload Timer/Counter (TL0).
TL0 is an 8-bit Timer/Counter.
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.
1
1
3
Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-
ister) with a modulo 32 prescaler implemented with the lower five bits of TL0 register
(see Figure 32). The upper three bits of TL0 register are indeterminate and should be
ignored. Prescaler overflow increments TH0 register. Figure 33 gives the overflow
period calculation formula.
66
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
