Data Reading/Writing
The NFDAT and NFDATF registers allow reading or writing of a byte without the use of
the DFC as detailed in the Section “Data Unit”. It launches an immediate read or write
NF cycle, depending if the software reads or writes in those registers.
Note:
•
The ECC is also computed when byte are read or written via NFDAT or NFDATF.
A write in NFDAT or NFDATF will produce an immediate “write cycle” (the NF
signals will be asserted accordingly) to store the byte given by the CPU.
Assembly code: mov direct, #
NFCLK / 2
NFCEx
NFCLE
NFALE
NFWE
NFRE
NFD[7:0]
Write data
•
A read of NFDATF or NFADC returns to the CPU the byte contained in that register
and launches in background a new “read cycle” (the NF signals will be asserted
accordingly). Once the “read cycle” is completed, the byte is held in the NFDAT and
NFDATF or NFADC registers. (The NFC stays in the running state (NFRUN set) as
long as the “read cycle” is not performed).
Note:
The NFADC register is particularly suitable to read and poll the nand flash(es) status
register.
Depending on the Nand Flash manufacturer, read cycle waveform may differ on the
NFRE pulse width parameter. In order to be compliant with all memories, NFRE read
pulse width can be programmed using TRS bit in NFCON according to Table 194.
Table 194. Read Cycle Configuration
TRS
Description
[1.5; 0.5] Cycle
0
NFRE asserted during 1.5 clock period and deasserted during 0.5 clock period.
[1.0;1.0] Cycle
1
NFRE asserted during 1 clock period and deasserted during 1 clock period.
174
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
