Figure 13. Reset Circuitry and Power-On Reset
IOVDD
RRST
RST
+
RST
To CPU Core
and Peripherals
N
IOVSS
From Internal
Reset Source
IOVSS
RST input circuitry
Power-on Reset
Cold Reset
2 conditions are required before enabling a CPU start-up:
•
•
VDD must reach the specified VDD range
The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be asserted till both of the above conditions are met. A
reset is active when the level VIL is reached and when the pulse width covers the period
of time where VDD and the oscillator are not stabilized. 2 parameters have to be taken
into account to determine the reset pulse width:
•
•
VDD rise time,
Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog Timer Reset
As detailed in Section “Watchdog Timer”, page 75, the WDT generates a 96-clock
period pulse on the RST pin. In order to properly propagate this pulse to the rest of the
application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resis-
tor must be added as shown in Figure 14.
Figure 14. Reset Circuitry for WDT Reset-out Usage
To Other
On-board
Circuitry
IOVDD
RRST
RST
1K
To CPU Core
and Peripherals
+
N
From WDT
Reset Source
IOVSS
IOVSS
Power Fail Detector
The Power Fail Detector (PFD) ensures that whole product is in reset when internal volt-
age is out of its limits specification. PFD limits are detailed in the Section “DC
Characteristics”, page 241.
24
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
