Bit
Bit
Number
Mnemonic Description
High Voltage Detect Flag
6
HVDET
-
Set by hardware when 3V is detected on HVDD pin.
Cleared by hardware when 3V is not detected on HVDD pin.
Reserved
5-3
The value of these bits is always 0. Do not set these bits.
Watchdog Timer Reset Flag
Set by hardware when the watchdog timer has overflowed triggering and internal
reset.
Must be cleared by software at power-up.
2
1
0
WDTRST
EXTRST
PFDRST
External Reset Flag
Set by hardware when the external RST pin is asserted (warm reset).
Must be cleared by software at power-up.
Power Failure Detector Reset Flag
Set by hardware when the power voltage has been triggered outside its specified
value (cold reset).
Must be cleared by software at power-up.
Reset Value = XX00 0XXXb(1)
Note:
1. Reset value depends on the power supply presence and on the internal reset source.
Table 22. VBAT Register
VBAT (0.85h) – Battery Voltage Monitor Register
7
6
5
4
3
2
1
0
VBEN
VBERR
-
VB4
VB3
VB2
VB1
VB0
Bit
Bit
Number
Mnemonic Description
Battery Monitor Enable Bit
Set to enable the battery monitoring.
7
VBEN
Cleared by hardware at the end of conversion
Battery Monitor Error Flag
6
5
VBERR
-
Set by hardware when conversion is out of min/max values.
Reserved
The value read from this bit is always 0. Do not set this bit.
Battery Value
4-0
VB4:0
Refer to Table 18 for voltage value correspondence.
Reset Value = 0000 0000b
26
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
