AT85C51SND3Bx
Registers
Table 20. PCON Register
PCON (0.87h) – Power Control Register
7
6
5
4
3
2
1
0
VBCEN
VBPEN
DCPBST
GF0
DCEN
PMLCK
PD
IDL
Bit
Bit
Number
Mnemonic Description
Battery Monitor Clock Enable Bit
7
6
5
4
VBCEN
VBPEN
DCPBST
GF0
Set to enable the clock of the battery monitoring.
Clear to disable the clock of the battery monitoring.
Battery Monitor Power Enable Bit
Set to power the battery monitoring.
Clear to unpower the battery monitoring.
DC-DC Converter Power Boost Bit
Set to disable DC-DC high power boost mode.
Clear to enable DC-DC high power boost mode.
General-purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
DC-DC Converter Enable Bit
Set to start the DC-DC converter or maintain its activity while DCPWR pin is
3
DCEN
asserted.
Clear to stop the DC-DC converter and shut off the device if not powered by an
external power supply.
Power Mode Lock Bit
Set to lock power-down or Idle mode entry by preventing PD or IDL bits from
being set by software.
Clear to unlock power-down or Idle mode entry.
2
1
0
PMLCK
PD
Power-down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode when PMLCK is cleared.
If IDL and PD are both set, PD takes precedence.
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode when PMLCK is cleared.
If IDL and PD are both set, PD takes precedence.
IDL
Reset Value = 00011 0000b
Table 21. PSTA Register
PSTA (0.86h) – Power Status Register
7
6
5
4
3
2
1
0
UVDET
HVDET
-
-
-
WDTRST
EXTRST
PFDRST
Bit
Bit
Number
Mnemonic Description
USB Voltage Detect Flag
Set by hardware when 5V is detected on UVDD pin.
Cleared by hardware when 5V is not detected on UVDD pin.
7
UVDET
25
7632A–MP3–03/06
ATMEL [ ATMEL ]
