Table 97. DFD0 Register
DFD0 (1.8Ah) – DFC Channel 0 Data Flow Descriptor Register
7
6
5
4
3
2
1
0
DFD0D7
DFD0D6
DFD0D5
DFD0D4
DFD0D3
DFD0D2
DFD0D1
DFD0D0
Bit
Bit
Number
Mnemonic Description
Channel 0 Data Flow Descriptor Data
Write data flow descriptor to this register as detailed in Table 91.
Read to get the remaining number of data packet after a delayed abort. MSB is
read first.
7-0
DFD0D7:0
Reset Value = 0000 0000b
Table 98. DFD1 Register
DFD1 (1.8Bh) – DFC Channel 1 Data Flow Descriptor Register
7
6
5
4
3
2
1
0
DFD1D7
DFD1D6
DFD1D5
DFD1D4
DFD1D3
DFD1D2
DFD1D1
DFD1D0
Bit
Bit
Number
Mnemonic Description
Channel 1 Data Flow Descriptor Data
Write data flow descriptor to this register as detailed in Table 91.
Read to get the remaining number of data packet after a delayed abort. MSB is
read first.
7-0
DFD1D7:0
Reset Value = 0000 0000b
Table 99. DFCRC Register
DFCRC (1.8Ch) – DFC CRC Data Register
7
6
5
4
3
2
1
0
CRCD7
CRCD6
CRCD5
CRCD4
CRCD3
CRCD2
CRCD1
CRCD0
Bit
Bit
Number
Mnemonic Description
CRC 2-byte Data FIFO
First reading of DFCRC returns the MSB of the CRC16 data while second
CRCD7:0 reading returns the LSB.
7-0
First writing to DFCRC writes the MSB of the initial value of the CRC16 data
while second writing writes the LSB.
Reset Value = 0000 0000b
84
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
