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85C51SND3B1 参数 Datasheet PDF下载

85C51SND3B1图片预览
型号: 85C51SND3B1
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片数字音频解码器 - 编码器与USB 2.0接口 [Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface]
分类和应用: 解码器编码器
文件页数/大小: 263 页 / 3620 K
品牌: ATMEL [ ATMEL ]
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AT85C51SND3Bx  
Bit  
Bit  
Number  
Mnemonic Description  
Channel 0 Destination Ready Flag  
Set by hardware when the source peripheral of channel 0 is ready.  
Cleared by hardware when the source peripheral of channel 0 is not ready.  
3
2
1
0
DRDY0  
SRDY0  
EOFI0  
Channel 0 Source Ready Flag  
Set by hardware when the destination peripheral of channel 0 is ready.  
Cleared by hardware when the destination peripheral of channel 0 is not ready.  
Channel 0 End Of Data Flow Interrupt Flag  
Set by hardware at the end of a channel 0 data flow transfer.  
Cleared by software by setting EOFIA0 in DFCCON. Can not be set by software.  
Channel 0 Busy Flag  
DFBSY0  
Set by hardware when a transfer is on-going on channel 0.  
Cleared by hardware when no transfer is on-going on channel 0.  
Reset Value = 0000 0000b  
Table 96. DFCCON Register  
DFCCON (1.85h) – DFC Channel Control Register  
7
6
5
4
3
2
1
0
DFABT1  
EOFE1  
EOFIA1  
-
DFABT0  
EOFE0  
EOFIA0  
-
Bit  
Bit  
Number  
Mnemonic Description  
Channel 1 Abort Control Bit  
7
6
DFABT1  
EOFE1  
Set to trigger an abort on channel 1.  
This bit is cleared by hardware.  
Channel 1 End Of Data Flow Interrupt Enable Bit  
Set to enable channel 1 EOF interrupt.  
Clear to disable channel 1 EOF interrupt.  
Channel 1 End Of Flow Interrupt Acknowledge Bit  
Set to acknowledge the channel 1 EOF interrupt (clear EOFI1 flag).  
Clearing this bit has no effect.  
5
EOFIA1  
The value read from this bit is always 0.  
Reserved  
4
3
-
The value read from this bit is always 0. Do not set this bit.  
Channel 0 Abort Control Bit  
DFABT0  
Set to trigger an abort on channel 0.  
This bit is cleared by hardware.  
Channel 0 End Of Data Flow Interrupt Enable Bit  
2
EOFE0  
Set to enable channel 0 EOF interrupt.  
Clear to disable channel 0 EOF interrupt.  
Channel 0 End Of Flow Interrupt Acknowledge Bit  
Set to acknowledge the channel 0 EOF interrupt (clear EOFI0 flag).  
Clearing this bit has no effect.  
The value read from this bit is always 0.  
1
0
EOFIA0  
-
Reserved  
The value read from this bit is always 0. Do not set this bit.  
Reset Value = 0000 0000b  
83  
7632A–MP3–03/06  
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