AT8xC51SND2C
Table 88. AUDSTA Register
AUDSTA (S:9Ch Read Only) – Audio Interface Status Register
7
6
5
4
-
3
-
2
-
1
-
0
-
SREQ
UDRN
AUBUSY
Bit
Bit
Number
Mnemonic Description
Audio Sample Request Flag
Set in C51 audio source mode when the audio interface request samples (buffer
half empty). This bit generates an interrupt if not masked and if enabled in IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
7
6
SREQ
UDRN
Audio Sample Under-run Flag
Set in C51 audio source mode when the audio interface runs out of samples
(buffer empty). This bit generates an interrupt if not masked and if enabled in
IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
Audio Interface Busy Bit
Set in C51 audio source mode when the audio interface can not accept more
sample (buffer full).
Cleared by hardware when buffer is no more full.
5
AUBUSY
-
Reserved
4 - 0
The value read from these bits is always 0. Do not set these bits.
Reset Value = 1100 0000b
Table 89. AUDDAT Register
AUDDAT (S:9Dh) – Audio Interface Data Register
7
6
5
4
3
2
1
0
AUD7
AUD6
AUD5
AUD4
AUD3
AUD2
AUD1
AUD0
Bit
Bit
Number
Mnemonic Description
Audio Data
8-bit sampling data for voice or sound playing.
7 - 0
AUD7:0
Reset Value = 1111 1111b
Table 90. AUDCLK Register
AUDCLK (S:ECh) – Audio Clock Divider Register
7
-
6
-
5
-
4
3
2
1
0
AUCD4
AUCD3
AUCD2
AUCD1
AUCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4 - 0
-
The value read from these bits is always 0. Do not set these bits.
Audio Clock Divider
5-bit divider for audio clock generation.
AUCD4:0
Reset Value = 0000 0000b
79
4341D–MP3–04/05
ATMEL [ ATMEL ]
