Registers
Table 86. AUDCON0 Register
AUDCON0 (S:9Ah) – Audio Interface Control Register 0
7
6
5
4
3
2
1
0
JUST4
JUST3
JUST2
JUST1
JUST0
POL
DSIZ
HLR
Bit
Bit
Number
Mnemonic Description
Audio Stream Justification Bits
Refer to Section "Data Converter", page 74 for bits description.
7 - 3
2
JUST4:0
POL
DSEL Signal Output Polarity
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I2S mode).
Audio Data Size
1
0
DSIZ
HLR
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
High/Low Rate Bit
Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
Reset Value = 0000 1000b
Table 87. AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
7
6
5
4
3
-
2
1
0
SRC
DRQEN
MSREQ
MUDRN
DUP1
DUP0
AUDEN
Bit
Bit
Number
Mnemonic Description
Audio Source Bit
Set to select C51 as audio source for voice or sound playing.
Clear to select the MP3 decoder output as audio source for song playing.
7
6
5
4
SRC
MP3 Decoded Data Request Enable Bit
DRQEN Set to enable data request to the MP3 decoder and to start playing song.
Clear to disable data request to the MP3 decoder.
Audio Sample Request Flag Mask Bit
MSREQ Set to prevent the SREQ flag from generating an audio interrupt.
Clear to allow the SREQ flag to generate an audio interrupt.
Audio Sample Under-run Flag Mask Bit
MUDRN Set to prevent the UDRN flag from generating an audio interrupt.
Clear to allow the UDRN flag to generate an audio interrupt.
Reserved
3
-
The value read from this bit is always 0. Do not set this bit.
Audio Duplication Factor
DUP1:0
2 - 1
Refer to Table 85 for bits description.
Audio Interface Enable Bit
AUDEN Set to enable the audio interface.
Clear to disable the audio interface.
0
Reset Value = 1011 0010b
78
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
