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5962-10A0301QYC 参数 Datasheet PDF下载

5962-10A0301QYC图片预览
型号: 5962-10A0301QYC
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor Circuit, CMOS, PBGA349, LGA-349]
分类和应用: 外围集成电路
文件页数/大小: 21 页 / 393 K
品牌: ATMEL [ ATMEL ]
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and one DAC device in parallel. Address and data signals unused by the ADC and the  
DAC can be use for general purpose input output, providing 0, 8, 16 or 24 channels.  
The ADC interface supports 8 and 16 bit data widths. It provides chip select, read/con-  
vert and ready signals. The timing is programmable. It also provides an 8-bit address  
output. The ADC conversion can be initiated either via the AMBA interface or by internal  
or external triggers. An interrupt is generated when a conversion is completed.  
The DAC interface supports 8 and 16 bit data widths. It provides a write strobe signal.  
The timing is programmable. It also provides an 8-bit address output.  
4.7  
4.8  
32-bit Timers  
The SpaceWire-RTC includes a General Purpose Timer Unit that implements one pres-  
caler and two 32-bit decrementing timers.  
24-bit General Purpose Input Output  
The SpaceWire-RTC includes a 24-bit General Purpose Input Output core. The AMBA  
APB bus is used for control and status handling.  
The core provides 24 channels. Each channel is individually programmed as input or  
output. Additionally, 8 of the channels are also programmable as pulse command out-  
puts. The default reset configuration for each channel is as input. The default reset  
value each channel is logical zero.  
The pulse command outputs have a common 20-bit counter for establishing the pulse  
command length. The pulse command length defines the logical one (active) part of the  
pulse. It is possible to select which of the channels shall generate a pulse command.  
The pulse command outputs are generated simultaneously in phase with each other,  
and with the same length (or duration). It is not possible to generate pulse commands  
out of phase with each other.  
4.9  
CAN Interface  
The SpaceWire-RTC includes a CAN controller. The CAN protocol is based on the ESA  
HurriCANe CAN Controller VHDL core.  
The controller uses the AMBA APB bus for configuration, control and status handling.  
The AMBA AHB bus is used for retrieving and storing CAN messages in memory exter-  
nal to the CAN controller. This memory can be located on-chip or external to the chip.  
The CAN controller supports transmission and reception of sets of messages by use of  
circular buffers located in memory external to the core. Separate transmit and receive  
buffers are assumed. Reception and transmission of sets of messages can be ongoing  
simultaneously.  
4.10 SpaceWire Link Interface  
The SpaceWire (SPW2) Module is used for transmitting and receiving data over a  
SpaceWire link. It provides support for transmitting any type of protocol or data structure  
using SpaceWire packets.  
12  
AT7913E  
7833F–AERO–01/10