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5962-10A0301QYC 参数 Datasheet PDF下载

5962-10A0301QYC图片预览
型号: 5962-10A0301QYC
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor Circuit, CMOS, PBGA349, LGA-349]
分类和应用: 外围集成电路
文件页数/大小: 21 页 / 393 K
品牌: ATMEL [ ATMEL ]
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AT7913E  
4.3.3  
4.3.4  
UART Serial Links  
Two identical UARTs are provided for serial communications. The UARTs support data  
frames with 8 data bits, one optional parity bit and one stop bit. To generate the bit-rate,  
each UART has a programmable 12-bits clock divider. Hardware flow-control is sup-  
ported through handshake signals.  
16-bit General Purpose Input Output  
The 16-bit general purpose input output port can be individually programmed as output  
or input. Two registers are associated with the operation of the port; the combined  
input/output register, and direction register. When read, the input/output register will  
return the current value of the port; when written, the value will be driven on the port sig-  
nals. The direction register defines the direction for each individual port.  
4.3.5  
Memory Interface  
The SpaceWire-RTC memory interface is implemented using the LEON2-FT Memory  
Controller that supports the following:  
• 8-bit PROM with sequential EDAC,  
• 8-bit SRAM with sequential EDAC  
• 32-bit PROM/SRAM with parallel-EDAC  
• 8, 16, 32 bit I/O without-EDAC (wait-state and/or ready handshake)  
• 16 bit GPIO (byte-wise) when less than 32 bit memory used  
4.4  
On-Chip Memory  
The SpaceWire-RTC device includes a fault tolerant on-chip SRAM with embedded  
Error Detection And Correction (EDAC) and AMBA AHB slave interface.  
One error is corrected and two errors are detected, which is done by using a (32, 7)  
BCH code. Some of the features available are single error counter, diagnostic reads and  
writes and auto-scrubbing (automatic correction of single errors during reads).  
The on-chip memory comprises a 32-bit wide memory bank of 64 kbytes of data.  
4.5  
4.6  
FIFO Interface  
This FIFO memory can be accessed as an on-chip memory or as an external interface  
of the chip via the Memory Interface.  
The FIFO interface supports transmission and reception of blocks of data by use of cir-  
cular buffers located in memory external to the core. Separate transmit and receive  
buffers are assumed. Reception and transmission of data can be ongoing  
simultaneously.  
ADC/DAC Interface  
The SpaceWire-RTC includes a combined analogue-to-digital converter (ADC) and digi-  
tal-to-analogue converter (DAC) interface.  
The ADC/DAC interface provides a combined signal interface to parallel ADC and DAC  
devices. The two interfaces are merged both at the pin/pad level as well as at the inter-  
face towards the AMBA bus. The interface supports simultaneously one ADC device  
11  
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