TS68EN360
Table of Contents
Features .................................................................................................... 1
Description ............................................................................................... 1
Screening/Quality
1
1
Introduction .............................................................................................. 2
1.1 QUICC Architecture Overview ..................................................................................2
2
3
Pin Assignments ...................................................................................... 3
Signal Description ................................................................................... 5
3.1 Functional Signal Group ...........................................................................................5
3.2 Signal Index ..............................................................................................................6
4
5
Detailed Specification ............................................................................ 11
Applicable Documents .......................................................................... 11
5.1 Design and Construction ........................................................................................11
5.2 Absolute Maximum Ratings ....................................................................................11
5.3 Power Considerations ............................................................................................12
5.4 Mechanical and Environment .................................................................................13
5.5 Marking ...................................................................................................................13
6
7
Quality Conformance Inspection .......................................................... 13
6.1 DESC/MIL-STD-883 ...............................................................................................13
Electrical Characteristics ...................................................................... 13
7.1 General Requirements ...........................................................................................13
7.2 Static Characteristics ..............................................................................................14
7.3 Dynamic Characteristics .........................................................................................14
7.4 AC Power Dissipation .............................................................................................16
7.5 AC Electrical Specifications Control Timing ...........................................................17
7.6 External Capacitor For PLL ....................................................................................18
7.7 Bus Operation AC Timing Specifications ................................................................19
7.8 Bus Operation – DRAM Accesses AC Timing Specification ..................................35
7.9 040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications ................39
7.10 040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical
Specifications ................................................................................................40
7.11 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications ........................43
7.12 IDMA AC Electrical Specifications ........................................................................49
i
2113B–HIREL–06/05
ATMEL [ ATMEL ]
