TS68EN360
7.18 SCC in NMSI Mode-external Clock Electrical Specifications
Table 7-17. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-51 to Figure 7-53)
25.0 MHz
Min
33.34 MHz
Min
Number Characteristic
Max
–
Max
–
Unit
100(1)
RCLK1 and TCLK1 Width High
CLKO1
CLKO1
101
RCLK1 and TCLK1 Width Low
CLKO1 + 5 ns
–
CLKO1 + 5 ns
–
102
RCLK1 and TCLK1 Rise/Fall Time
–
0
15
50
50
–
–
0
15
50
50
–
ns
ns
ns
ns
ns
ns
ns
103
TXD1 Active Delay (From TCLK1 Falling Edge)
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
CTS1 Setup Time to TCLK1 Rising Edge
RXD1 Setup Time to RCLK1 Rising Edge
RXD1 Hold Time from RCLK1 Rising Edge
CD1 Setup Time to RCLK1 Rising Edge
104
0
0
105
40
40
0
40
40
0
106
–
–
107(2)
–
–
108
40
–
40
–
Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1.
2. Also applies to CD and CTS hold time when they are used as external sync signals.
7.19 SCC in NMSI Mode-internal Clock Electrical Specifications
Table 7-18. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-51 to Figure 7-53)
25.0 MHz
Min
33.34 MHz
Number Characteristic
Max
8.3
–
Min
Max
11
–
Unit
100(1)
RCLK1 and TCLK1 Frequency
0
–
0
–
MHz
ns
102
RCLK1 and TCLK1 Rise/Fall Time
103
TXD1 Active Delay (From TCLK1 Falling Edge)
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
CTS1 Setup Time to TCLK1 Rising Edge
RXD1 Setup Time to RCLK1 Rising Edge
RXD1 Hold Time from RCLK1 Rising Edge
CD1 Setup Time to RCLK1 Rising Edge
0
30
30
–
0
30
–
ns
104
0
40
40
0
ns
105
40
40
0
–
ns
106
–
–
ns
107(2)
–
40
0
–
ns
108
40
–
30
ns
Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
2. Also applies to CD and CTS hold time when they are used as external sync signals.
61
2113B–HIREL–06/05
ATMEL [ ATMEL ]
