Figure 7-49. SI Transmit Timing with Double Speed Clocking (DSC = 1)
72
83A
L1RCLK
(FE = 0,
CE = 0)
(INPUT)
82
L1RCLK
(FE = 1,
CE = 1)
(INPUT)
75
L1TSYNC
(INPUT)
73
74
TFCD = 0
81
80A
L1TXD
(OUTPUT)
BIT0
80
78A
79
L1ST (1-4)
(OUTPUT)
78
L1CLKO
(OUTPUT)
84
Figure 7-50. IDL Timing SI Transmit Timing with Double Speed Clocking (DSC = 1)
74
L1RSYNC
(INPUT)
73
71
L1RCLK
(INPUT)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
M
71
80
L1TXD
(OUTPUT)
B17
B16
B15 B14 B13 B12 B11 B10 D1
72
A
A
B27 B26 B25 B24 B23 B22 B21 B20 D2
81
77
76
L1RXD
(INPUT)
B17
B16
B15 B14 B13 B12 B11 B10 D1
78
B27 B26 B25 B24 B23 B22 B21 B20 D2
M
L1ST (4-1)
(OUTPUT)
85
L1RQ
(OUTPUT)
86
87
L1GR
(INPUT)
60
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
