Figure 7-28. TS68040 IACK Cycles (Vector Driven)
C1
C2
CW
CW
CW
CW
CW
CLKO1
(OUTPUT)
251
254
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
263
258
(INPUT)
262
259
D31-D0
(OUTPUT)
260
TA
(OUTPUT)
257
TBI
(OUTPUT)
IACK7-1
(OUTPUT)
266
267
0Ð2 CLOCKS
Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
2. Up to two wait states may be inserted for internal peripheral.
Figure 7-29. TS68040 IACK Cycles (No Vector Driven)
C1
C2
CW
CW
254
CLKO1
(OUTPUT)
251
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
(INPUT)
290
TA
(INPUT)
289
TBI
(OUTPUT)
257
250
265
AVECO
(OUTPUT)
264
IACK7-1
(OUTPUT)
266
267
Note:
TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
42
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
