TS68EN360
Figure 7-26. TS68040 Internal Registers Read Cycles
C1
C2
CW
CW
CW
CW
C1
CLKO1
(OUTPUT)
251
A31-A0
(INPUT)
254
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
(INPUT)
260
263
D31-D0
(040 WRITE)
(INPUT)
TA
(OUTPUT)
258
257
259
TBI
(OUTPUT)
3Ð4 CLOCKS
Notes: 1. Three wait states are inserted when reading the SIM, dual-port RAM, and CPM. Four wait states are inserted when reading
the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is
accessing an internal peripheral.
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
Figure 7-27. TS68040 Internal Registers Write Cycles
C1
C2
CW
CW
CW
C1
CLKO1
(OUTPUT)
251
A31-A0
(INPUT)
254
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
(INPUT)
256
255
D31-D0
(040 WRITE)
(INPUT)
256
255
MBARE
(INPUT)
258
TA
(OUTPUT)
257
259
TBI
(OUTPUT)
2Ñ4 CLOCKS
Notes: 1. Two wait states are inserted when writing. Three wait states are inserted when writing to the dual-port RAM and CPM. Four
wait states are inserted when writing to the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10
and one of the internal masters is accessing an internal peripheral.
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
41
2113B–HIREL–06/05
ATMEL [ ATMEL ]
