7.17 SI Electrical Specifications
Table 7-16. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary
(See Figure 7-46 to Figure 7-50)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
10
–
Min
Max
10
–
Unit
MHz
ns
70(1)(3)
71(1)
71A(2)
72
L1RCLK, L1TCLK Frequency (DCS = 0)
–
P+10
P+10
–
–
P+10
P+10
–
L1RCLK, L1TCLK Width Low (DCS = 0)
L1RCLK, L1TCLK Width High (DCS = 0)
L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time
L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time)
L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time)
L1RSYNC, L1TSYNC Rise/Fall Time
L1RXD Valid to L1CLK Edge (L1RXD Setup Time)
L1CLK Edge to L1RXD Invalid (L1RXD Hold Time)
L1CLK Edge to L1ST(1-4) Valid
–
–
ns
15
–
15
–
ns
73
20
35
–
20
35
–
ns
74
–
–
ns
75
15
–
15
–
ns
76
42
35
10
10
10
10
10
0
42
35
10
10
10
10
10
0
ns
77
–
–
ns
78
45
45
45
65
65
42
12.5
–
45
45
45
65
65
42
16
–
ns
78A(4)
L1SYNC Valid to L1ST(1-4) Valid
ns
79
L1CLK Edge to L1ST(1-4) Invalid
ns
80
L1CLK Edge to L1TXD Valid
ns
80A(4)
L1TSYNC Valid to L1TXD Valid
ns
81
L1CLK Edge to L1TXD High Impedance
L1RCLK, L1TCLK Frequency (DSC = 1)
L1RCLK, L1TCLK Width Low (DSC = 1)
L1RCLK, L1TCLK Width High (DSC = 1)
L1CLK Edge to L1CLKO Valid (DSC = 1)
L1RQ Valid Before Falling Edge of L1TSYNC
L1GR Setup Time
ns
82
–
–
MHz
ns
83
P+10
P+10
–
P+10
P+10
–
83A(2)
–
–
ns
84
30
–
30
–
ns
85(3)
86(3)
87(3)
1
1
L1TCLK
ns
42
42
–
42
42
–
L1RG Hold Time
–
–
ns
L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0,
DSC = 0)
88
–
0
–
0
ns
Notes: 1. The ratio SyncCLK/L1RC LK must be greater than 2.5/1.
2. Where P = 1/CLKO1. Thus for a 25 MHz CLKO1 rate, P = 40 ns.
3. These specs are valid for IDL mode only.
4. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
56
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
