Table 7-6.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-3 to Figure 7-19) (Continued)
25 MHz
33.34 MHz
Number
Characteristic
Symbol
Min
Max
Min
Max
Unit
83
DSCLC Hold Time
tDSCH
6
–
–
3.75
–
–
ns
tcyc+2
0
tcyc+2
0
84
DSO Delay Time
tDSOD
ns
85
86
87
88
89
90
91
92
DSCLK Cycle
tDSCCYC
tFRZA
tFRZN
tIFZ
2
0
0
0
0
0
0
5
–
2
0
0
0
0
0
0
5
–
CLKO1
ns
CLKO1 High to Freeze Asserted
CLKO1 High to Freeze Negated
CLKO1 High to IFETCH High Impedance
CLKO1 High to IFETCH Valid
CLKO1 High to PERR Asserted
CLKO1 High to PERR Negated
VCC Ramp-Up Time At Power-On Reset
35
35
35
35
20
20
–
26.25
26.25
26.25
26.25
15
ns
ns
tIF
ns
tCHPA
tCHPN
tRMIN
ns
15
ns
–
ns
Notes: 1. All AC timing is shown with respect to 0.8V and 2.0V levels unless otherwise noted.
2. This number can be reduced to 5 ns if strobes have equal loads.
3. If multiple chip selects are used, the CSx width negated (#15) applies to the time from the negation of a heavily loaded chip
select to the assertion of a lightly loaded chip select.
4. Hold times are specified with respect to DS or CSx on asynchronous reads and with respect to CLKO1 on fast termination
reads. The user is free to use either hold time for fast termination reads.
5. If the asynchronous setup (#17) requirements are satisfied, the DSACKx low to data setup time (#31) and DSACKx low to
BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKO1 low setup time (#27) for the fol-
lowing clock cycle: BERR must only satisfy the late BERR low to CLKO1 low setup time (#27A) for the following clock cycle.
6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the cur-
rent operand transfer are complete and RMC is negated.
7. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (#47).
8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1.
9. Specs are for Synchronous Arbitration only. ASTM = 1.
10. CSx specs are for TRLX = 0.
11. CSx specs are for TRLX = 1.
12. CSx specs are for CSNTQ = 0.
13. CSx specs are for CSNTQ = 1; or RASx specs for DRAM accesses.
14. Specs are read cycles with parity check and PBEE = 1.
15. Specs are read cycles with parity check and PBEE = 0, PAREN = 1.
16. RASx specs are for page miss case.
17. Specifications only apply to CSx/RASx pins.
18. Specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated by 20 ns
after negation of AS, DS.
22
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
