R suffix
PGA 241
A suffix
CERQUAD 240
Ceramic Pin Grid Array Cavity Up
Ceramic Leaded Chip Carrier Cavity Down
1. Introduction
1.1
QUICC Architecture Overview
The QUICC is 32-bit controller that is an extension of other members of the TS68300 family.
Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB).
The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common inter-
face for all modules of the TS68300 family, which allows the development of new devices more
quickly by using the library of existing modules. Although the IMB definition always included an
option for an on-chip 32-bit bus, the QUICC is the first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each
module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in Figure 1-1.
Figure 1-1. QUICC Block Diagram
SIM 60
JTAG
SYSTEM
PROTECTION
BREAKPOINT
LOGIC
PERIODIC
TIMER
CPU32+
CORE
CLOCK
GENERATION
DRAM
CONTROLLER
AND
OTHER
FEATURES
CHIP SELECTS
SYSTEM
I/F
EXTERNAL
BUS
IMB (32 BIT)
INTERFACE
CPM
COMMUNICATIONS PROCESSOR
2.5-KBYTE
DUAL-PORT
RAM
RISC
CONTROLLER
FOUR
GENERAL-
PURPOSE
TIMERS
TWO
IDMAs
FOURTEEN SERIAL
DMAs
INTERRUPT
CONTROLLER
SEVEN
SERIAL
CHANNELS
OTHER
FEATURES
TIMER SLOT
ASSIGNER
2
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
