Figure 2.
Reset (write (read) to Programmable Half Full Flag register)
Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.
Data set-up and hold times must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any
current read operation.
Once half the memory is filled, and during the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to low and remain in this state until the difference
between the write and read pointers is less than or equal to half of the total available
memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the
read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-
tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,
allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is
blocked from W, so that external changes to W will have no effect on the full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the
Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including
any current write operations. After Read Enable (R) goes high, the Data Outputs
(Q0 - Q8) will return to a high impedance state until the next Read operation. When all
the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the
“final” read cycle, but inhibiting further read operations while the data outputs remain in
a high impedance state. Once a valid write operation has been completed, the Empty
Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO
stack is empty, the internal read pointer is blocked from R, so that external changes to R
will have no effect on the empty FIFO stack.
This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to
ground to indicate that it is the first loaded (see Operating Modes). In the Single Device
Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-
necting the Expansion In (XI) to ground.
The M672061H can be set to retransmit data when the Retransmit Enable Control (RT)
input is pulsed low. A retransmit operation will set the internal read point to the first loca-
tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be
in the high state during retransmit. The retransmit feature is intended for use when a
number of writes are equal to or less than the depth of the FIFO has occured since the
last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (HF), in accordance with the relative locations of the
read and write pointers.
First Load/Retransmit
(FL/RT)
4
M672061H
4144K-AERO-04/07
ATMEL [ ATMEL CORPORATION ]
