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5962-9161706QZC 参数 Datasheet PDF下载

5962-9161706QZC图片预览
型号: 5962-9161706QZC
PDF下载: 下载PDF文件 查看货源
内容描述: 弧度。宽容高速8 KB ×16双端口RAM [Rad. Tolerant High Speed 8 Kb x 16 Dual Port RAM]
分类和应用:
文件页数/大小: 27 页 / 528 K
品牌: ATMEL [ ATMEL ]
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the logic will assign the token arbitrarily to one of the ports. It should be noted, however,  
that semaphores alone do not guarantee that access to a resource is secure. As with  
any powerful programming technique, errors can be introduced if semaphores are mis-  
used or misinterpreted. Code integrity is of the utmost performance when semaphores  
are being used instead of slower, more restrictive hardware-intensive systems.  
Semaphore initialization is not automatic and must therefore be incorporated in the  
power up initialization procedures. Since any semaphore flag containing a zero must be  
reset to one, initialization should write a one to all request flags from both sides to  
ensure that they will be available when required.  
Using Semaphores –  
Some Examples  
Perhaps the simplest application of semaphores is their use as resource markers for the  
M67025E’s dual-port RAM. If it is necessary to split the 8 Kb × 16 RAM into two 4 Kb × 16  
blocks which are to be dedicated to serving either the left or right port at any one time. Sema-  
phore 0 can be used to indicate which side is controlling the lower segment of memory and  
semaphore 1 can be defined as indicating the upper segment of memory.  
To take control of a resource, in this case the lower 4 Kb of a dual-port RAM, the left port  
processor would then write a zero into semaphore flag 0 and then read it back. If suc-  
cessful in taking the token (reading back a zero rather than a one), the left processor  
could then take control of the lower 4 Kb of RAM. If the right processor attempts to per-  
form the same function to take control of the resource after the left processor has  
already done so, it will read back a one in response to the attempted write of a zero into  
semaphore 0. At this point the software may choose to attempt to gain control of the  
second 4 Kb segment of RAM by writing and then reading a zero in semaphore 1. If suc-  
cessful, it will lock out the left processor.  
Once the left side has completed its task it will write a one to semaphore 0 and may then  
attempt to access semaphore 1. If semaphore 1 is still occupied by the right side, the left  
side may abandon its semaphore request and perform other operations until it is able to  
write and then read a zero in semaphore 1. If the right processor performs the same  
operation with semaphore 0, this protocol would then allow the two processes to swap  
4 Kb blocks of dual-port RAM between one another.  
The blocks do not have to be any particular size, and may even be of variable size  
depending on the complexity of the software using the semaphore flags. All eight sema-  
phores could be used to divide the dual-port RAM or other shared resources into eight  
parts. Semaphores can even be assigned different meanings on each side, rather than  
having a common meaning as is described in the above example.  
Semaphores are a useful form of arbitration in systems such as disk interfaces where  
the CPU must be locked out of a segment of memory during a data transfer operation,  
and the I/0 device cannot tolerate any wait states. If semaphores are used, both the  
CPU and the I/0 device can access assigned memory segments, without the need for  
wait states, once the two devices have determined which memory area is barred to the  
CPU.  
Semaphores are also useful in applications where no memory WAIT state is available  
on one or both sides. On a semaphore handshake has been performed, both proces-  
sors can access their assigned RAM segments at full speed.  
Another application is in complex data structures. Block arbitration is very important in  
this case, since one processor may be responsible for building and updating a data  
structure whilst the other processor reads and interprets it. A major error condition may  
be created if the interpreting processor reads an incomplete data structure. Some sort of  
arbitration between the two different processors is therefore necessary. The building  
processor requests access to the block, locks it and is then able to enter the block to  
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M67025E  
4146J–AERO–06/03  
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