AC Busy Characteristics
Table 9. AC Electrical Characteristics
Over the Full Operating Temperature and Supply Voltage Range
M
M
67025-30
67025-45
Write Cycle
Parameter
Min.
Max.
Min.
Max.
Unit
Busy Timing (For Master 67025 only)
BUSY Access time
to address
tBAA
–
–
–
–
30
25
25
20
–
–
–
–
35
30
30
25
ns
ns
ns
ns
BUSY Disable time
to address
tBDA
BUSY Access time
to Chip Select
tBAC
BUSY Disable time
to Chip Select
tBDC
tWDD
tDDD
tAPS
tBDD
tWB
Write Pulse to data Delay (1)
–
–
55
40
–
–
70
55
ns
ns
ns
ns
ns
ns
ns
ns
Write data valid to read data delay(1)
Arbitration priority set-up time (2)
BUSY disable to valid data
Write to BUSY input (4)
5
–
5
–
(3)
(3)
–
–
0
–
–
0
–
–
tWH
Write hold after BUSY (5)
20
–
25
–
tWDD
tDDD
Write pulse to data delay (6)
Write data valid to read data delay(6)
55
40
70
55
–
–
1.
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For Mas-
ter 67025 only)’.
2.
3.
4.
5.
6.
To ensure that the earlier of the two ports wins.
t
BDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) to tDDD - tDW (actual).
To ensure that the write cycle is inhibited during contention.
To ensure that a write cycle is completed after contention.
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)’.
17
M67025E
4146J–AERO–06/03
ATMEL [ ATMEL ]
