AT22V10/L
Preload of Registered Outputs
The registers in the AT22V10 and AT22V10L are provided
with circuitry to allow loading of each register asynchro-
nously with either a high or a low. This feature will simplify
testing since any state can be forced into the registers to
Level forced on
registered output pin
during preload cycle
Register state
after cycle
control test sequencing. A V level on the I/O pin will
IH
V
V
High
IH
force the register high; a V will force it low, independent
IL
Low
of the polarity bit (C0) setting. The preload state is entered
by placing an 11.5-V to 13-V signal on pin 8 on DIPs, and
pin 10 on SMPs. When the clock pin is pulsed high, the
data on the I/O pins is placed into the ten registers.
IL
t
= 100 ns
DMIN
Power Up Reset
The registers in the AT22V10 and AT22V10L are de-
signed to reset during power up. At a point delayed slightly
from V
crossing 3.8 V, all registers will be reset to the
CC
low state. The output state will depend on the polarity of
the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how V actually rises in the system, the fol-
CC
lowing conditions are required:
1) The V rise must be monotonic,
CC
Description
Parameter
Min Typ Max Units
2) After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and
Power-Up
Reset Time
t
600 1000
ns
PR
3) The clock must remain stable during t
.
PR
1-103
ATMEL [ ATMEL ]
